1. Field of the Invention
The present invention relates to a negative feedback variable gain amplifier circuit preferably used in AGC (Automatic Gain Control) circuits of wireless receivers or the like.
2. Description of Related Art
Recently, with the development of radiophones or the like, wide dynamic range, high linearity variable gain amplifier circuits have been urgently required which convert a received signal of dynamically varying amplitude into a signal of nearly a constant level.
FIG. 1 shows a conventional negative feedback amplifier circuit. The negative amplifier circuit includes an amplifier 1, and a feedback circuit 3 consisting of a capacitor 3a and a resistor 3b. An input matching circuit 7 is connected between the amplifier 1 and an input port 5, and an output matching circuit 9 is connected between the amplifier 1 and an output port 11.
The feedback circuit 3 presents a problem in that it transmits an input signal from the input side to the output side of the amplifier 1 because of its reciprocal characteristic. In particular, the problem becomes serious when the gain of the amplifier 1 is less than unity, in which the effect of the transmitted signal component on the output side increases through the feedback circuit 3.
FIGS. 2 and 3 show conventional variable gain amplifier circuits. The variable gain amplifier circuit of FIG. 2 employs a dual gate FET 21 as an amplifier, and utilizes one of the dual gate terminals as a control port 23 to implement a variable gain amplifier circuit. In addition, a gate bias voltage Vg is applied to the gate terminal of an FET constituting the input matching circuit 7 through a gate bias port 27, and a drain bias voltage Vdd is applied to the drain terminal of an FET constituting the output matching circuit 9 through a drain bias port 29.
The variable gain amplifier circuit of FIG. 3 has a cascode amplifier composed of FETs 31 and 33, and uses the gate terminal of the FET 33 as a control port 35, thereby implementing a variable gain amplifier circuit. The variable gain amplifier circuits of FIGS. 2 and 3 are equivalent in that the transconductances of the FETs are changed to control their gains.
In FIG. 3, when the gain of the amplifier circuit must be increased to amplify a low level input signal, the transconductance g.sub.m of the FET 31 is increased by applying a larger percentage of the voltage across FETs 31 and 33 between the drain of FET 31 and ground. This is achieved by applying a positive voltage to the control port 35. In contrast with this, when the gain of the amplifier circuit must be decreased to amplify (attenuate) a high level input signal, the transconductances g.sub.m of the FETs 31 and 33 are reduced. This is achieved by applying a negative voltage to the control port 35, thereby reducing the voltage between the drain of the FET 31 and ground, and increasing the a reverse bias between the source and gate of the FET 33.
Generally, the linearity of an FET is considerably degraded with the reduction of its transconductance. As a result, in the variable gain amplifier circuit which varies its gain by changing the transconductances of the FETs, the amplitude of the FET 31 sharply drops and the linearity of the FET 33 is considerably degraded during the low gain operation. This poses a problem in that the maximum allowable input level to the amplifier circuit drops as the gain is reduced in response to a large amplitude input signal. In other words, it has a drawback in that its low distortion range is narrow.
FIG. 4 shows an amplifier circuit developed for solving the drawbacks of the foregoing variable gain amplifier circuits, which was presented in the IEEE MTT-S International Microwave Symposium in 1991. This amplifier circuit employs a common source FET 41 as an amplifier, and a serial circuit of a capacitor 43a and an FET 43b as a feedback circuit. The gate terminal of the FET 43b is grounded through a bypass capacitor 45, and is connected to a control port 47. The gain of the amplifier circuit is controlled by varying the resistance across the drain and source of the FET 43b.
According to this variable gain amplifier circuit, since the drain bias voltage of the FET 41 which operates as an amplifier is kept constant, the low distortion range increases as compared with the variable gain amplifier circuit of FIG. 3. In addition, the input impedance of the amplifier is decreased as the drain-source resistance of the FET 43b is reduced to drop the gain of the amplifier in response to an increase in the amplitude of the input signal. Thus, the voltage level applied to the gate of the FET 41 is suppressed, and hence the maximum allowable input level can be increased.
It is important for the variable gain amplifier circuit to vary its input impedance in a wider range to accomplish a low distortion operation up to a larger input signal level.
FIG. 5 illustrates the relationship between the gate control voltage and the drain-source resistance Rds of the feedback FET 43b of FIG. 4. The gate width of the FET 43b is 100 .mu.m. In this case, the minimum resistance of the FET 43b is several tens of ohms. As a result, the minimum gain of the amplifier circuit of FIG. 4 is limited to approximately -10 dB. To further decrease the minimum gain of the amplifier circuit, it is necessary to further reduce the drain-source resistance of the feedback FET 43b. For this purpose, the gate width of the FET 43b must be widened. This, however, presents another problem in that the parasitic capacitance increases, and this degrades the performance of the amplifier (that is, the gain-bandwidth product).
FIG. 6 shows another conventional feedback amplifier circuit which is disclosed in SU543133. The amplifier circuit comprises a two-stage amplifier including transistors 51 and 53, and a feedback transistor 52. The base of the feedback transistor 52 is connected to the collector of the output transistor 53 through a resistor 54, and to the base of the output transistor 53 through a capacitor 55. The emitter of the feedback transistor 52 is connected to the base of the output transistor 53 through a resistor 56. An unstable voltage component at the collector of the output transistor 53 causes a current in the base of the feedback transistor 52 through the resistor 54. The current is amplified by the feedback FET 52, and is supplied to the base of the output transistor 53 through the resistor 56, thereby compensating for the instability of the collector. Thus, the output loss of the output transistor 53 is reduced, and the maximum output signal is increased.
In the negative feedback amplifier circuit of FIG. 6, however, the output transistor 53 and the feedback transistor 52 are integrated, and cannot be controlled independently. Therefore, the gain of the amplifier circuit cannot be varied externally.
FIG. 7 shows still another negative feedback amplifier circuit by Kobayashi, which is disclosed in U.S. Pat. No. 5,264,806. The amplifier circuit includes a Darlington amplifier 62 and an active feedback circuit 64. The active feedback circuit 64 includes a transistor QF, and resistors Rte and Rbt. The base of the transistor QF is connected to the output terminal of the Darlington amplifier 62 via the resistor Rbt, and the emitter thereof is connected to the input terminal of the Darlington amplifier 62 through the resistor RF. In this amplifier circuit, it is possible to vary the inductance of the active feedback circuit 64 by changing the resistances of the resistors Rbt and Rte, thereby varying the bandwidth of the amplifier circuit. The transistor QF of the active feedback circuit 64, however, cannot operate independently of the Darlington amplifier 62. Accordingly, the gain of the amplifier cannot be controlled externally.
FIG. 8 shows a conventional negative feedback variable gain amplifier circuit presented in Electronics Letters, 14th Sep., 1989, Vol. 25, No. 19, pp. 1317-1318. The amplifier circuit is a differential amplifier. In this figure, major amplifying portions comprise transistors Q1 and Q2, and each of the transistors Q3 constitutes a negative feedback circuit. Specifically, the base of each of the feedback transistors Q3 is connected to the output terminal of one of the output transistors Q2, and the emitter of each of the feedback transistors Q3 is connected to the input terminal of one of the output transistors Q2 via a resistor RL1. Using the transistors Q3 as the feedback circuits makes it possible to widen the bandwidth of the variable gain amplifier circuit. In addition, the variable gain amplifier circuit varies its gain by changing the transconductance of the transistor Q1.
In the negative feedback variable gain amplifier circuit, however, the feedback transistors Q3 cannot operate independently of the major amplifying portion, and hence gain control by controlling the feedback amount is impossible. Furthermore, since the gain is controlled by varying the transconductance of the transistor Q1 in the major amplifying portion, it has the above-mentioned drawbacks. That is, the amplification factor of the transistor Q1 is sharply reduced and linearity thereof is considerably degraded when the gain of the variable gain amplifier circuit is low. Thus, the amplifier circuit has drawbacks in that the maximum allowable input level for low-distortion operation is rather low because it is reduced with a decrease in the gain.
In summary:
(1) The maximum allowable input level is limited in the variable gain amplifier circuits shown in FIGS. 2 and 3 because of the poor linearity of their amplifiers.
(2) The maximum allowable input level is limited in the variable gain amplifier circuit shown in FIG. 4 because of the physical dimension of the FETs constituting the variable gain amplifier circuit.
(3) The gain cannot be controlled in the negative feedback amplifier circuits shown in FIGS. 6 and 7, because the feedback transistors cannot operate independently of the major amplifying portions.
(4) The gain cannot be controlled in the negative feedback variable gain amplifier circuit shown in FIG. 8, because the feedback transistor cannot operate independently of the major amplifying portion. In addition, the maximum allowable input level is limited because of the poor linearity of the amplifier.